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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:19:48 02/04/2009 
-- Design Name: 
-- Module Name:    reset_module - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity reset_module is
    Port (	reset_button : in  STD_LOGIC;
				locked_48k : in std_logic;
				locked_40M : in std_logic;
				reset : out  STD_LOGIC;
				hard_reset : out  STD_LOGIC
				);
end reset_module;

architecture Behavioral of reset_module is
	signal counter			: integer 	:= 0;
begin

	reset <= reset_button and locked_48k and locked_40M;
	hard_reset <= reset_button;
	
end Behavioral;

